The present invention relates to a semiconductor device, and a failure detection system and a failure detection method of a data hold circuit, and in particular, a semiconductor device, and a failure detection system and a failure detection method of a data hold circuit detecting a failure in the data hold circuit mounted on the semiconductor device, the data hold circuit including a plurality of flip-flop circuits or the like.
Along with a miniaturization of a chip in an area of the semiconductor device, the semiconductor device including a flip-flop circuit may be easily influenced by alpha rays, which results in malfunction. Hence, it is general to increase alpha-ray-resistance strength of a logic circuit by using a majority logic circuit including a plurality of flip-flop circuits for preventing the malfunction caused by the alpha rays. Further, in recent years, the miniaturization of a chip has been advancing, more and more semiconductor devices have been including a plurality of flip-flop circuits, and the number of flip-flop circuits mounted on the semiconductor device has been increasing. Therefore, there has been a growing need to perform the failure detection of the flip-flop circuit itself.
Japanese Unexamined Patent Application Publication No. 2002-185309 discloses a technique relating to a data hold circuit including at least three flip-flop circuits, and a majority logic circuit to output a signal according to a logical value of a majority in output values of the three flip-flop circuits. The data hold circuit has a circuit configuration so as to improve the reliability of data holding. Even if the output value of any one flip-flop circuit has changed when the alpha rays pass through any of the three flip-flop circuits, the data hold circuit can keep a correct output signal by output values of other flip-flop circuits. Further, the data hold circuit can detect a hardware failure of the flip-flop circuit.
FIG. 11 is a block diagram showing a configuration of a data hold circuit according to Japanese Unexamined Patent Application Publication No. 2002-185309. An alpha ray assurance flip-flop circuit 900 shown in FIG. 11 includes three flip-flop circuits FF1 to FF3, and a majority logic circuit MJR. Each of the flip-flop circuits FF1 to FF3 receives the same input data D through an input terminal TI1. The majority logic circuit MJR outputs a signal having the same logic as the output of the majority of output signals of the flip-flop circuits FF1 to FF3, that is, two or more flip-flop circuits having the same logic among the three flip-flop circuits.
The alpha ray assurance flip-flop circuit 900 outputs an output signal Q received from the majority logic circuit MJR through an output terminal TO1. Each of the flip-flop circuits FF1 to FF3 receives different clock signals CK1 to CK3 through input terminals TI2 to TI4. Each of the flip-flop circuits FF1 to FF3 is configured to receive and hold each of signals of the input data D in synchronization with the clock signals CK1 to CK3.
For example, by the alpha rays passing through any one of the flip-flop circuits FF1 to FF3, latch data held by the flip-flop circuit through which the alpha rays pass might invert. Even in this case, it is possible to prevent malfunction of the alpha ray assurance flip-flop circuit 900. This is because the inverted data is a minority value, thereby the majority logic circuit MJR ignores a change of the signal caused by the alpha rays.
Note that, the three clock signals CK1 to CK3 are supplied at the same timing, and can be generated, for example, by distributing an original clock signal by a plurality of clock buffers or the like. In this way, by separating the clock signals to latch each of the flip-flop circuits FF1 to FF3, it can prevent malfunction of the alpha ray assurance flip-flop circuit 900, even if noise caused by the alpha rays is generated in either one of clock signals. This is because there is only one flip-flop circuit in which an output signal is changed by the noise and the majority logic circuit MJR cuts a change of the signal by the noise.
FIG. 12 is a block diagram showing a configuration of flip-flop circuits which can realize a scan test according to Japanese Unexamined Patent Application Publication No. 2002-185309. A scan test circuit 900a shown in FIG. 12 is capable of performing a scan test compared with the configuration of the alpha ray assurance flip-flop circuit 900. The scan test circuit 900a includes three flip-flop circuits FF1a to FF3a, and the majority logic circuit MJR. Each of the flip-flop circuits FF1a to FF3a composes a scan pass for test. That is, the flip-flop circuits FF1a to FF3a have functions of scan-in and scan-out.
In particular, each of the flip-flop circuits FF1a to FF3a further receives different scan-in data SID1 to SID3 through input terminals TI5 to TI7, compared with the flip-flop circuits FF1 to FF3 of FIG. 11. Each of the flip-flop circuits FF1a to FF3a receives the same clock signal TM for scan through an input terminal TI8. Each of the flip-flop circuits FF1a to FF3a is configured to receive and hold each of signals of scan-in data SID1 to SID3 in synchronization with a clock signal TM for scan.
The scan test circuit 900a outputs scan-out data SOD1 to SOD3 received from the flip-flop circuits FF1a to FF3a through output terminals TO2 to TO4, respectively. Herewith, the scan test circuit 900a can transmit independent test values from the scan-in data SID1 to SID3 to the scan-out data SOD1 to SOD3 corresponding to each of the flip-flop circuits FF1a to FF3a. Therefore, it can test each of the flip-flop circuits FF1a to FF3a or the majority logic circuit MJR.
FIG. 13 is a diagram showing an operational truth table of the scan test circuit 900a shown in FIG. 12. SID1 to SID3 of FIG. 13 are values of holding statuses of the flip-flop circuits FF1a to FF3a. The value of Q of FIG. 13 is a value of the output signal Q of the majority logic circuit MJR.